Shoot-through and the VGS bump: understanding and calculating them in a half-bridge

Every motor drive, synchronous buck, inverter and full-bridge converter is built from half-bridges: a high-side switch and a low-side switch with the switch node between them. The rule is simple: never both on at once. The DC bus is then shorted through two channels, and the current is limited only by the MOSFET on-resistance and loop inductance. The result ranges from extra heat and EMI to an instant, loud failure.

What shoot-through looks like

Hard shoot-through: both devices fully on. The bus current spikes to hundreds of amps in nanoseconds. Usually destructive on the first event.
Soft (partial) shoot-through: one device is still in its turn-off tail, or the other is pulled briefly into its linear region. Each event dumps a little energy. You see it as "unexplained" switching loss, hot MOSFETs at light load, a current spike on every edge and ringing on the bus.

Soft shoot-through is the dangerous one, because the board works on the bench and fails later, hot, at high bus voltage or after a part change.

Cause 1: dead time shorter than the real turn-off time

The controller inserts a dead time: after commanding one switch off, it waits before commanding the other on. The question is how long the turning-off MOSFET really takes to stop conducting.

The gate does not switch off instantly. The driver pulls charge out of the gate through the total turn-off resistance:

R_off = R_driver(sink) + R_G(external, off path) + R_G(internal)

and the gate voltage falls in three phases:

From the drive voltage down to the Miller plateau. The channel is still fully on.
Along the Miller plateau. The drain voltage swings while the gate stays flat, because the driver is busy discharging the gate-drain capacitance (charge Q_gd).
From the plateau down to the threshold `V_th`. The current falls to zero. Only below V_th is the device really off.

A first-order estimate of the time to reach "off":

t1 = R_off · C_iss · ln(V_drive / V_plateau)

t2 = Q_gd / I_G, with I_G = V_plateau / R_off

t3 = R_off · C_iss · ln(V_plateau / V_th)

t_off ≈ t1 + t2 + t3

Worked example: dead time

A 100 V MOSFET in a 48 V bridge, driven at 12 V:

Parameter	Value	Where it comes from
`C_iss`	5 nF	datasheet, at the operating V_DS
`Q_gd`	12 nC	gate-charge curve, plateau width at 48 V
`V_plateau`	4.5 V	gate-charge curve, at your load current
`V_th` (min, hot)	1.9 V	2.5 V min at 25 °C, about −6 mV/°C to 125 °C
`R_off`	4.2 Ω	0.5 Ω driver sink + 2.2 Ω external + 1.5 Ω internal

t1 = 4.2 Ω × 5 nF × ln(12 / 4.5) = 21 ns × 0.98 ≈ 21 ns
I_G = 4.5 V / 4.2 Ω ≈ 1.07 A, so t2 = 12 nC / 1.07 A ≈ 11 ns
t3 = 21 ns × ln(4.5 / 1.9) = 21 ns × 0.86 ≈ 18 ns
`t_off ≈ 50 ns`

Then add what the gate maths does not see:

Propagation-delay mismatch between the high-side and low-side driver channels (often 5–20 ns, from the driver datasheet; more with isolators or level shifters).
Tolerance margin for part spread, temperature and supply variation (×1.3 to ×1.5 is typical).

t_dead ≥ (t_off + Δt_prop) × margin = (50 + 10) ns × 1.5 ≈ 90 ns, so choose 100 ns.

Cause 2: the VGS bump (dv/dt-induced turn-on)

Even with perfect dead time, the low-side MOSFET can be turned on while its driver is holding it off.

When the high-side switch turns on, the switch node rises from 0 V to the bus voltage in a few nanoseconds. The low-side MOSFET's drain rises with it. Its gate-drain capacitance C_gd couples that edge into the gate. A current flows through C_gd:

i_gd = C_gd · dV_DS/dt

That current has to return to the source through the gate network: the turn-off resistance R_off in parallel with C_gs. The gate voltage therefore lifts, which is the VGS bump. If the peak crosses V_th, the low-side channel opens during the high-side turn-on: shoot-through, with the driver doing everything right.

Calculating the bump

C_gd is strongly nonlinear: tiny at high voltage, large near 0 V. Using the single C_rss value from the datasheet table under-estimates the bump. A more honest estimate uses charge, read from the gate-charge curve: the charge that has to move through C_gd for the full voltage swing is Q_gd at your bus voltage.

Average injected current: i_gd ≈ Q_gd / t_r, with t_r = V_bus / (dv/dt).
Gate RC time constant: τ = R_off · C_iss.
Peak bump (first-order RC charged by a constant current for t_r): ΔV_GS ≈ i_gd · R_off · (1 − e^(−t_r / τ))
Upper bound (no gate resistance helps at all): ΔV_GS ≤ Q_gd / C_iss.

The result always sits between two limits, and the ratio t_r / τ tells you which one is closer:

Charge (capacitive-divider) limit: when the edge is much faster than the gate loop (t_r ≪ τ), the gate simply shares the injected charge with C_iss: ΔV_GS → Q / (C_iss + C_GS,ext). No dv/dt can push the bump past this, because the charge is all there is.
Resistive limit: when the edge is slow compared with the gate loop (t_r ≫ τ), the bump is just the Miller current times the resistance: ΔV_GS → i_gd · R_off.

Quoting I · R alone on a fast, hard-switched bridge overstates the bump. Quoting the divider alone on a slow one understates it. The exponential expression above matches both limits.

If you need a target bump, size the external gate-source capacitor directly:

C_GS,ext = Q / ΔV_target − C_iss, with Q ≈ C_rss · V_bus (or Q_gd from the curve)

Worked example: the VGS bump

Switch node rising 48 V at 4 V/ns:

t_r = 48 V / 4 V/ns = 12 ns
i_gd = 12 nC / 12 ns = 1.0 A
τ = 4.2 Ω × 5 nF = 21 ns
ΔV_GS = 1.0 A × 4.2 Ω × (1 − e^(−12/21)) = 4.2 V × 0.435 ≈ 1.8 V
Upper bound: 12 nC / 5 nF = 2.4 V

Compared with V_th(min, hot) = 1.9 V, the margin is 0.1 V. On paper this board is already at the edge, and in practice ringing and source inductance will push it over. This is exactly the situation that "works on the bench, fails in the field".

What changes the result

Fix	New numbers	Bump	Margin to 1.9 V	Cost
Baseline	4.2 Ω, 4 V/ns	1.8 V	0.1 V	—
Low-impedance turn-off path (diode + 0 Ω), R_off → 2.0 Ω	τ = 10 ns	1.4 V	0.5 V	Faster turn-off, more ringing
Slower high-side turn-on (R_on up), 2 V/ns	t_r = 24 ns, i = 0.5 A, R_off = 2.0 Ω	0.9 V	1.0 V	Higher turn-on loss
Extra external C_GS 4.7 nF (with R_off = 2.0 Ω)	C = 9.7 nF, τ = 19 ns	0.9 V	1.0 V	Slower switching, more gate-drive power
Negative off-voltage −3 V	threshold effectively 4.9 V away	1.8 V	3.1 V	Bipolar supply, gate V_GS(min) rating
Active Miller clamp in the driver	gate held near 0 V by a low-Ω switch	≪ 1 V	large	Driver with clamp pin, layout close to the FET

The internal gate resistance (1.5 Ω here) sets a floor you cannot lay out away. That is why lowering the external resistor helps less than you might hope, and why clamps and negative bias exist.

Worked example: the gate-resistor trade-off

A common temptation on a high-current, low-voltage bridge is to "tidy up" the gate network: change the gate resistor and drop the small gate-source capacitor as redundant. The numbers show why that needs care. (Illustrative values, not a specific product.)

Take a 100 V MOSFET on an 80 V bus, with C_rss = 80 pF, C_iss = 4 nF, 1.5 Ω internal gate resistance, and a measured node dv/dt of 5 V/ns:

Quantity	Calculation	Result
Miller current (peak)	`C_rss · dv/dt = 80 pF × 5 V/ns`	0.4 A
Miller charge	`C_rss · V_bus = 80 pF × 80 V`	6.4 nC
Edge duration	`80 V / 5 V/ns`	16 ns
Gate time constant (8 Ω external)	`(8 Ω + 1.5 Ω) × 4 nF`	38 ns
Charge limit	`6.4 nC / 4 nF`	1.6 V
Resistive limit	`0.4 A × 9.5 Ω`	3.8 V
Bump	`3.8 V × (1 − e^(−16/38))`	1.3 V
V_th min at 125 °C	`2.0 V − 6 mV/K × 100 K` (tempco assumed)	1.4 V
Margin		≈ 0.1 V

On paper it does not quite conduct. In practice, with C_rss rising about 3:1 at low V_DS, ringing on the node and some common-source inductance, a 0.1 V margin is no margin.

Add a 1 nF gate-source capacitor and the charge limit falls to 6.4 nC / 5 nF = 1.28 V, the time constant rises to 47.5 ns, and the bump drops to about 1.1 V, a margin of 0.3 V. To hold the bump at 1.0 V you would need C_GS = 6.4 nC / 1.0 V − 4 nF ≈ 2.4 nF. That small capacitor is doing a real job.

The gate resistor cuts both ways:

Miller immunity: at a given dv/dt, the bump scales with gate resistance. Raising R_G to tame di/dt *raises* the bump, while lowering it speeds up every edge. The two requirements pull in opposite directions, and the gate-source capacitor is what breaks the tie.
Overvoltage: a faster turn-off interrupts the current faster. Interrupting 200 A in 30 ns is di/dt ≈ 6.7 A/ns, and a 3 nH commutation loop then adds L · di/dt = 20 V to the 80 V bus. That is the full 100 V rating with no margin left. Halve the turn-off time and the spike doubles. Removing the drain-source snubber makes it worse, because the loop energy ½ L I² then has only the MOSFETs' output capacitance to charge.

With several MOSFETs in parallel on one driver there is one more limit: the driver can only move charge so fast (t ≥ N · Q_g / I_peak). Below that, changing the gate resistor no longer changes the edge speed the way a single-device calculation suggests.

The safe direction is usually the opposite of the tidy-up:

Keep a gate-source capacitor sized from the formula above.
Use the smallest drain-source snubber that still damps the ringing; large snubbers burn ½ C V² f in every capacitor.
Set turn-off speed so the inductive spike stays well below the voltage rating.

The hidden term: common-source inductance

The gate loop and the power loop often share a few millimetres of source lead, bond wire or copper. That shared common-source inductance L_cs adds a voltage to the gate whenever the drain current changes:

V_Lcs = L_cs · di/dt

With only 1 nH and 2 A/ns that is 2 V, the same size as the whole VGS bump above. Its sign can lift the gate of the off device or slow down the device that is switching. Fixes:

Use MOSFETs with a Kelvin source pin, and return the gate driver to it.
Route gate and gate-return as a tight pair, directly to the MOSFET pins, away from the power loop.
Keep the power loop (bus capacitor → high-side → low-side) as small as possible, ideally stacked on adjacent layers.

Measuring it, not guessing

Probe V_GS directly at the MOSFET pins with a short ground spring, or better with a high-CMRR isolated or differential probe. A long ground lead adds its own "bump" and makes good boards look bad.
Trigger on the switch-node edge and look at the off device's gate during the other device's turn-on.
Watch the bus current or the bus capacitor ripple (Rogowski coil or a shunt) for a spike on every edge: the signature of soft shoot-through.
Test hot. V_th drops with temperature, so the margin is smallest at maximum junction temperature and maximum bus voltage.

Design checklist

Calculate t_off from the gate network and set dead time from it, including driver mismatch and margin. Do not copy a number from another design.
Use the hot, minimum V_th, not the typical 25 °C value.
Calculate the VGS bump at your real dv/dt and bus voltage, with Q_gd from the gate-charge curve.
Give the turn-off path a lower resistance than the turn-on path (separate resistors plus a diode, or a driver with split outputs).
Choose a driver with a Miller clamp or negative bias for fast, high-voltage bridges (SiC and GaN need this almost always).
Keep common-source inductance out of the gate loop: Kelvin source, tight gate routing, small power loop.
Verify on the bench, at temperature, with proper probing, and trim dead time last.

Working on a half-bridge design?

IDEAS designs and validates motor drives, chargers and power converters, from gate-drive calculations to layout and bench validation. If a bridge is running hot or failing for no obvious reason, talk to us.